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LTC3809 1 3809fc typical application features applications description no r sense ?, low emi, synchronous dc/dc controller the ltc ? 3809 is a synchronous step-down switching regu- lator controller that drives external complementary power mosfets using few external components. the constant frequency current mode architecture with mosfet v ds sensing eliminates the need for a current sense resistor and improves ef? ciency. for noise sensitive applications, the LTC3809 can be exter- nally synchronized from 250khz to 750khz. burst mode is inhibited during synchronization or when the sync/mode pin is pulled low to reduce noise and rf interference. to further reduce emi, the LTC3809 incorporates a novel spread spectrum frequency modulation technique. burst mode operation provides high ef? ciency operation at light loads. 100% duty cycle provides low dropout operation, extending operating time in battery-powered systems. the switching frequency can be programmed up to 750khz, allowing the use of small surface mount inductors and capacitors. the LTC3809 is available in tiny footprint thermally enhanced dfn and 10-lead msop packages. high ef? ciency, 550khz step-down converter n no current sense resistor required n selectable spread spectrum frequency modulation for low noise operation n constant frequency current mode operation for excellent line and load transient response n true pll for frequency locking or adjustment (frequency range: 250khz to 750khz) n wide v in range: 2.75v to 9.8v n wide v out range: 0.6v to v in n 0.6v 1.5% reference n low dropout operation: 100% duty cycle n selectable burst mode ? /pulse-skipping/forced continuous operation n auxiliary winding regulation n internal soft-start circuitry n output overvoltage protection n micropower shutdown: i q = 9a n tiny thermally enhanced leadless (3mm 3mm) dfn and 10-lead msop packages n 1- or 2-cell lithium-ion powered devices n portable instruments n distributed dc power systems l , lt, ltc, ltm and burst mode are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5929620, 6580258, 6304066, 5847554, 6611131, 6498466. other patents pending. LTC3809 2.2h 10f v in 2.75v to 9.8v v out 2.5v 2a 47f 3809 ta01 15k 59k 187k 470pf gnd plllpf sync/mode v fb i th run sw v in tg bg iprg load current (ma) efficiency (%) 100 90 80 70 60 50 power loss (mw) 10k 1k 100 10 1 0.1 1 100 1000 10000 3809 ta01b 10 v in = 3.3v v in = 5v v in = 4.2v figure 10 circuit v out = 2.5v power loss v in = 4.2v efficiency ef? ciency and power loss vs load current
LTC3809 2 3809fc absolute maximum ratings input supply voltage (v in ) ........................ ? 0.3v to 10v plllpf, run, sync/mode, iprg voltages ............................... ? 0.3v to (v in + 0.3v) v fb , i th voltages ...................................... ? 0.3v to 2.4v sw voltage ......................... ? 2v to v in + 1v (10v max) tg, bg peak output current (<10s) ......................... 1a (note 1) pin configuration operating temperature range (note 2)....? 40c to 85c storage temperature range ...................? 65c to 125c junction temperature (note 3) ............................ 125c lead temperature (soldering, 10 sec) msop package ................................................. 300c top view 11 dd package 10-lead (3mm s 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 sw v in tg bg iprg plllpf sync/mode v fb i th run t jmax = 125c, ja = 43c/w exposed pad (pin 11) is gnd (must be soldered to pcb) 1 2 3 4 5 plllpf sync/mode v fb i th run 10 9 8 7 6 sw v in tg bg iprg top view 11 mse package 10-lead plastic msop t jmax = 125c, ja = 40c/w exposed pad (pin 11) is gnd (must be soldered to pcb) lead free finish tape and reel part marking package description temperature range LTC3809edd#pbf LTC3809edd#trpbf lbqy 10-lead (3mm 3mm) plastic dfn ? 40c to 85c LTC3809emse#pbf LTC3809emse#trpbf ltbqt 10-lead plastic msop ? 40c to 85c lead based finish tape and reel part marking package description temperature range LTC3809edd LTC3809edd#tr lbqy 10-lead (3mm 3mm) plastic dfn ? 40c to 85c LTC3809emse LTC3809emse#tr ltbqt 10-lead plastic msop ? 40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ order information
LTC3809 3 3809fc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 4.2v unless otherwise noted. parameter conditions min typ max units main control loops input dc supply current normal operation sleep mode shutdown uvlo (note 4) run = 0v v in = uvlo threshold C 200mv 350 105 9 3 500 150 20 10 a a a a undervoltage lockout threshold (uvlo) v in falling v in rising l l 1.95 2.15 2.25 2.45 2.55 2.75 v v shutdown threshold of run pin 0.8 1.1 1.4 v regulated feedback voltage (note 5) l 0.591 0.6 0.609 v output voltage line regulation 2.75v < v in < 9.8v (note 5) 0.01 0.04 %/v output voltage load regulation i th = 0.9v (note 5) i th = 1.7v 0.1 C0.1 0.5 C0.5 % % v fb input current (note 5) 9 50 na overvoltage protect threshold measured at v fb 0.66 0.68 0.7 v overvoltage protect hysteresis 20 mv auxiliary feedback threshold 0.325 0.4 0.475 v top gate (tg) drive rise time c l = 3000pf 40 ns top gate (tg) drive fall time c l = 3000pf 40 ns bottom gate (bg) drive rise time c l = 3000pf 50 ns bottom gate (bg) drive fall time c l = 3000pf 40 ns maximum current sense voltage ( v sense(max) ) (v in C sw) iprg = floating (note 6) iprg = 0v (note 6) iprg = v in (note 6) l l l 110 70 185 125 85 204 140 100 223 mv mv mv soft-start time (internal) time for v fb to ramp from 0.05v to 0.55v 0.5 0.74 0.9 ms oscillator and phase-locked loop oscillator frequency unsynchronized (sync/mode not clocked) plllpf = floating plllpf = 0v plllpf = v in 480 260 650 550 300 750 600 340 825 khz khz khz phase-locked loop lock range sync/mode clocked minimum synchronizable frequency maximum synchronizible frequency 750 200 1000 250 khz khz phase detector output current sinking sourcing f osc > f sync/mode f osc < f sync/mode C3 3 a a spread spectrum frequency range minimum switching frequency maximum switching frequency 460 635 khz khz sync/mode pull-down current sync/mode = 2.2v 2.6 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3809e is guaranteed to meet speci? ed performance from 0c to 85c. speci? cations over the C40c to 85c operating range are assured by design characterization, and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja c/w) note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency. note 5: the LTC3809 is tested in a feedback loop that servos i th to a speci? ed voltage and measures the resultant v fb voltage. note 6: peak current sense voltage is reduced dependent on duty cycle to a percentage of value as shown in figure 1.
LTC3809 4 3809fc typical performance characteristics ef? ciency vs load current maximum current sense voltage vs i th pin voltage load step (burst mode operation) load step (pulse-skipping mode) start-up with internal soft-start t a = 25c unless otherwise noted. load current (ma) efficiency (%) 100 90 80 70 95 85 75 65 60 1 100 1k 10k 3809 g01 10 v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.2v figure 10 circuit sync/mode = v in v in = 5v load current (ma) efficiency (%) 100 90 80 70 95 85 75 65 50 55 60 3809 g02 1 100 1k 10k 10 figure 10 circuit v in = 5v, v out = 2.5v forced continuous (sync/mode = 0v) pulse skipping (sync/mode = 0.6v) burst mode (sync/mode = v in ) i th voltage (v) 0.5 C20 current limit (%) 0 20 40 60 100 1 1.5 3809 g03 2 80 burst mode operation (i th rising) burst mode operation (i th falling) forced continuous mode pulse skipping mode ef? ciency vs load current v out 200mv/div ac coupled i l 2a/div 100s/div v in = 3.3v v out = 1.8v i load = 300ma to 3a sync/mode = v in figure 10 circuit 3809 g04 v out 200mv/div ac coupled i l 2a/div 100s/div v in = 3.3v v out = 1.8v i load = 300ma to 3a sync/mode = 0v figure 10 circuit 3809 g05 load step (forced continuous mode) v out 200mv/div ac coupled i l 2a/div 100s/div v in = 3.3v v out = 1.8v i load = 300ma to 3a sync/mode = v fb figure 10 circuit 3809 g06 v out 1.8v 500mv/div 200s/div v in = 4.2v r load = 1 figure 10 circuit 3809 g07
LTC3809 5 3809fc typical performance characteristics regulated feedback voltage vs temperature undervoltage lockout threshold vs temperature shutdown (run) threshold vs temperature maximum current sense threshold vs temperature sync/mode pull-down current vs temperature oscillator frequency vs temperature oscillator frequency vs input voltage shutdown quiescent current vs input voltage sleep current vs input voltage t a = 25c unless otherwise noted. temperature (c) C60 0.594 feedback voltage (v) 0.596 0.598 0.600 0.602 C20 20 60 100 3809 g08 0.604 0.606 C40 0 40 80 temperature (c) C60 2.15 2.20 2.25 input voltage (v) 2.30 2.35 2.40 2.45 C20 20 60 100 3809 g09 2.50 2.55 C40 0 40 80 v in rising v in falling temperature (c) C60 1.00 run voltage (v) 1.05 C20 20 60 100 3809 g10 1.15 1.10 1.20 C40 0 40 80 temperature (c) C60 115 maximum current sense threshold (mv) 120 125 130 C20 20 60 100 3809 g11 135 C40 0 40 80 iprg = float temperature (c) C60 2.40 2.45 2.50 sync/mode pull-down current (a) 2.55 2.60 2.65 2.70 C20 20 60 100 3809 g12 2.75 2.80 C40 0 40 80 temperature (c) C60 C10 C8 C6 normalized frequency (%) C4 C2 0 4 C20 20 60 100 3809 g13 8 2 6 10 C40 0 40 80 input voltage (v) 2 C5 C4 C3 normalized frequency shift (%) C2 C1 0 2 46 8 10 3809 g14 4 1 3 5 35 7 9 input voltage (v) 2 0 2 shutdown current (a) 4 6 8 12 46 8 10 3809 g15 16 10 14 18 35 7 9 input voltage (v) 2 70 sleep current (a) 80 100 46 8 10 3809 g16 120 90 110 130 35 7 9
LTC3809 6 3809fc pin functions plllpf (pin 1): frequency set/pll lowpass filter. when synchronizing to an external clock, this pin serves as the lowpass ? lter point for the phase-locked loop. normally, a series rc is connected between this pin and ground. w h e n n o t s y n c h r o n i z i n g t o a n e x t e r n a l c l o c k , t h i s p i n s e r v e s as the frequency select input. tying this pin to gnd selects 300khz operation; tying this pin to v in selects 750khz operation. floating this pin selects 550khz operation. connect a 2.2nf capacitor between this pin and gnd, and a 1000pf capacitor between this pin and the sync/mode when using spread spectrum modulation operation. sync/mode (pin 2): this pin performs four functions: 1) auxiliary winding feedback input, 2) external clock synchronization input for phase-locked loop, 3) burst mode, pulse-skipping or forc ed continuous mode select, and 4) enable spread spectrum modulation operation in pulse-skipping mode. applying a clock with frequency between 250khz to 750khz causes the internal oscillator to phase-lock to the external clock and disables burst mode operation but allows pulse-skipping at low load currents. to select burst mode operation at light loads, tie this pin to v in . grounding this pin selects forced continuous operation, which allows the inductor current to reverse. tying this pin to v fb selects pulse-skipping mode. in these cases, the frequency of the internal oscillator is set by the voltage on the plllpf pin. tying to a voltage between 1.35v to v in C 0.5v enables spread spectrum modulation o p e r a t i o n . i n t h i s c a s e , a n i n t e r n a l 2 . 6 a p u l l - d o w n c u r r e n t source helps to set the voltage at this pin by tying a resistor with appropriate value between this pin and v in . do not leave this pin ? oating. v fb (pin 3): feedback pin. this pin receives the remotely sensed feedback voltage for the controller from an external resistor divider across the output. ith (pin 4): current threshold and error ampli? er compensation point. nominal operating range on this pin is from 0.7v to 2v. the voltage on this pin determines the threshold of the main current comparator. run (pin 5): run control input. forcing this pin below 1.1v shuts down the chip. driving this pin to v in or releas- ing this pin enables the chip to start-up with the internal soft-start. iprg (pin 6): three-state pin to select maximum peak sense voltage threshold. this pin selects the maximum allowed voltage drop between the v in and sw pins (i.e., the maximum allowed drop across the external p-channel mosfet). tie to v in , gnd or ? oat to select 204mv, 85mv or 125mv respectively. bg (pin 7): bottom (nmos) gate drive output. this pin drives the gate of the external n-channel mosfet. this pin has an output swing from pgnd to v in . tg (pin 8): top (pmos) gate drive output. this pin drives the gate of the external p-channel mosfet. this pin has an output swing from pgnd to v in . v in (pin 9): chip signal power supply. this pin powers the entire chip, the gate drivers and serves as the positive input to the differential current comparator. sw (pin 10): switch node connection to inductor. this pin is also the negative input to the differential current comparator and an input to the reverse current comparator. normally this pin is connected to the drain of the external p-channel mosfet, the drain of the external n-channel mosfet and the inductor. gnd (pin 11): exposed pad. the exposed pad is ground and must be soldered to the pcb ground for electrical contact and optimum thermal performance.
LTC3809 7 3809fc functional diagram C + C + C + C + C + slope sense + iprg clk icmp r s q anti-shoot- through gnd pv in tg bg ov uv i rev 0.68v 0.54v v fb fcb v ref 0.6v ss fcb sleep burstdis 0.15v v in 0.3v i th 3809 fd v fb r c c c sw l mp mn c out v out switching logic and blanking circuit r a r b C + + sw gnd C + eamp ricmp clk burstdis sync/mode plllpf i rev v co phase detector clock detect burst defeat t = 1ms internal soft-start run v in v in c in 2.6a 0.4v v in uvsd v ref 0.6v v in 0.7a undervoltage lockout voltage reference 9 6 5 gnd ss 11 2 1 8 10 7 4 3
LTC3809 8 3809fc operation (refer to functional diagram) main control loop the LTC3809 uses a constant frequency, current mode architecture. during normal operation, the top external p-channel power mosfet is turned on when the clock sets the rs latch, and is turned off when the current comparator (icmp) resets the latch. the peak inductor current at which icmp resets the rs latch is determined by the voltage on the i th pin, which is driven by the output of the error ampli? er (eamp). the v fb pin receives the output voltage feedback signal from an external resistor divider. this feedback signal is compared to the internal 0.6v reference voltage by the eamp. when the load cur- rent increases, it causes a slight decrease in v fb relative to the 0.6v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. while the top p-channel mosfet is off, the bottom n-channel mosfet is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator ircmp, or the beginning of the next cycle. shutdown and soft-start (run pin) the LTC3809 is shut down by pulling the run pin low. in shutdown, all controller functions are disabled and the chip draws only 9a. the tg output is held high (off) and the bg output low (off) in shutdown. releasing the run pin allows an internal 0.7a current source to pull up the run pin to v in . the controller is enabled when the run pin reaches 1.1v. the start-up of v out is controlled by the LTC3809s inter- nal soft-start. during soft-start, the error ampli? er eamp compares the feedback signal v fb t o t h e i n t e r n a l s o f t- s t a r t ramp (instead of the 0.6v reference), which rises linearly from 0v to 0.6v in about 1ms. this allows the output voltage to rise smoothly from 0v to its ? nal value while maintaining control of the inductor current. light load operation (burst mode operation, continuous conduction or pulse-skipping mode) (sync/mode pin) the LTC3809 can be programmed for either high ef? ciency burst mode operation, forced continuous conduction mode or pulse-skipping mode at low load currents. to select burst mode operation, tie the sync/mode pin to v in . to select forced continuous operation, tie the sync/mode pin to a dc voltage below 0.4v (e.g., gnd). tying the sync/mode to a dc voltage above 0.4v and below 1.2v (e.g., v fb ) enables pulse-skipping mode. the 0.4v threshold between forced continuous operation and pulse-skipping mode can be used in secondary winding regulation as described in the auxiliary winding control using sync/mode pin discussion in the applications information section. when the LTC3809 is in burst mode operation, the peak current in the inductor is set to approximately one-fourth of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the eamp will decrease the voltage on the i th pin. when the i th voltage drops below 0.85v, the internal sleep signal goes high and the external mosfet is turned off. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the LTC3809 draws. the load current is supplied by the output capacitor. as the output voltage decreases, the eamp increases the i th voltage. when the i th voltage reaches 0.925v, the sleep signal goes low and the controller resumes normal operation by turning on the external p-channel mosfet on the next cycle of the internal oscillator. when the controller is enabled for burst mode or pulse- skipping operation, the inductor current is not allowed to reverse. hence, the controller operates discontinuously.
LTC3809 9 3809fc operation (refer to functional diagram) the reverse current comparator ricmp senses the drain-to- source voltage of the bottom external n-channel mosfet. this mosfet is turned off just before the inductor current reaches zero, preventing it from going negative. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. the p-channel mosfet is turned on every cycle (constant frequency) regardless of the i th pin voltage. in this mode, the ef? ciency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and no noise at audio frequencies. when the sync/mode pin is clocked by an external clock source to use the phase-locked loop (see frequency selection and phase-locked loop), or is set to a dc voltage between 0.4v and several hundred mv below v in , the LTC3809 operates in pwm pulse-skipping mode at light loads. in this mode, the current comparator icmp may remain tripped for several cycles and force the external p-channel mosfet to stay off for the same number of cycles. the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operat ion. however, it provides low current ef? ciency higher than forced continuous mode, but not nearly as high as burst mode operation. during start-up or an undervoltage condition (v fb 0.54v), the LTC3809 operates in pulse-skipping mode (no current reversal allowed), regardless of the state of the sync/mode pin. short-circuit and current limit protection the LTC3809 monitors the voltage drop v sc (between the gnd and sw pins) across the external n-channel mosfet with the short-circuit current limit comparator. the allowed voltage is determined by: v sc(max) = a ? 90mv where a is a constant determined by the state of the iprg pin. floating the iprg pin selects a = 1; tying iprg to v in selects a = 5/3; tying iprg to gnd selects a = 2/3. the inductor current limit for short-circuit protection is determined by v sc(max) and the on-resistance of the external n-channel mosfet: i v r sc sc max ds on = () () once the inductor current exceeds i sc , the short current comparator will shut off the external p-channel mosfet until the inductor current drops below i sc . output overvoltage protection as further protection, the overvoltage comparator (ovp) g u a r d s a g a i n s t t r a n s i e n t o v e r s h o o t s , a s w e l l a s o t h e r m o r e serious conditions that may overvoltage the output. when the feedback voltage on the v fb pin has risen 13.33% above the reference voltage of 0.6v, the external p-chan- nel mosfet is turned off and the n-channel mosfet is turned on until the overvoltage is cleared.
LTC3809 10 3809fc operation (refer to functional diagram) frequency selection and phase-locked loop (plllpf and sync/mode pins) the selection of switching frequency is a tradeoff between ef? ciency and component size. low frequency operation increases ef? ciency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the LTC3809s controllers can be selected using the plllpf pin. if the sync/mode is not being driven by an external clock source, the plllpf can be ? oated, tied to v in or tied to gnd to select 550khz, 750khz or 300khz, respectively. a phase-locked loop (pll) is available on the LTC3809 to synchronize the internal oscillator to an external clock source that connects to the sync/ mode pin. in this case, a series rc should be connected between the plllpf pin and gnd to serve as the plls loop ? lter. the LTC3809 phase detector adjusts the voltage on the plllpf pin to align the turn-on of the external p-channel mosfet to the rising edge of the synchronizing signal. the typical capture range of the LTC3809s phase-locked loop is from approximately 200khz to 1mhz. spread spectrum modulation (sync/mode and plllpf pins) connecting the sync/mode pin to a dc voltage above 1.35v and several hundred mv below v in enables spread spectrum modulation (ssm) operation. an internal 2.6a pull-down current source at sync/mode helps to set the voltage at the sync/mode pin for this operation by tying a resistor with appropriate value between sync/mode and v in . this mode of operation spreads the internal oscillator frequency f osc (= 550khz) over a wider range (460khz to 635khz), reducing the peaks of the harmonic output on a spectral analysis of the output noise. in this case, a 2.2nf ? lter cap should be connected between the plllpf pin and gnd and another 1000pf cap should be connected between plllpf and the sync/mode pin. the controller operates in pwm pulse-skipping mode at light loads when spread spectrum modulation is selected. see the discussion of spread spectrum modulation with sync/mode and plllpf pins in the applications information section. dropout operation when the input supply voltage (v in ) approaches the output voltage, the rate of change of the inductor current while the external p-channel mosfet is on (on cycle) decreases. this reduction means that the p-channel mosfet will remain on for more than one oscillator cycle if the inductor current has not ramped up to the threshold set by the eamp on the i th pin. further reduction in the input supply voltage will eventually cause the p-channel mosfet to be turned on 100%; i.e., dc. the output voltage will then be determined by the input voltage minus the voltage drop across the p-channel mosfet and the inductor. undervoltage lockout to prevent operation of the p-channel mosfet below safe input voltage levels, an undervoltage lockout is incorporated in the LTC3809. when the input supply voltage (v in ) drops below 2.25v, the external p- and n-channel mosfets and all internal circuits are turned off except for the undervoltage block, which draws only a few microamperes.
LTC3809 11 3809fc operation (refer to functional diagram) peak current sense voltage selection and slope compensation (iprg pin) when the LTC3809 controller is operating below 20% duty cycle, the peak current sense voltage (between the v in and sw pins) allowed across the external p-channel mosfet is determined by: = va vv sense max ith () ? ?. 07 10 where a is a constant determined by the state of the iprg pin. floating the iprg pin selects a = 1; tying iprg to v in selects a = 5/3; tying iprg to gnd selects a = 2/3. the maximum value of v ith is typically about 1.98v, so the maximum sense voltage allowed across the external p- channel mosfet is 125mv, 85mv or 204mv for the three respective states of the iprg pin. however, once the controllers duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor (sf) given by the curve in figure 1. the peak inductor current is determined by the peak sense voltage and the on-resistance of the external p-channel mosfet: i v r pk sense max ds on = () () duty cycle (%) 10 sf = i/i max (%) 60 80 110 100 90 3809 f01 40 20 50 70 90 30 10 0 30 50 70 20 0 40 60 80 100 figure 1. maximum peak current vs duty cycle
LTC3809 12 3809fc applications information the typical LTC3809 application circuit is shown in fig- ure 10. external component selection for the controller is driven by the load requirement and begins with the selection of the inductor and the power mosfets. power mosfet selection the LTC3809s controller requires two external power mosfets: a p-channel mosfet for the topside (main) switch and a n-channel mosfet for the bottom (synchro- nous) switch. the main selection criteria for the power mosfets are the breakdown voltage v br(dss) , threshold voltage v gs(th) , on-resistance r ds(on) , reverse transfer capacitance c rss , turn-off delay t d(off) and the total gate charge q g . the gate drive voltage is the input supply voltage. since the LTC3809 is designed for operation down to low input voltages, a sublogic level mosfet (r ds(on) guaranteed at v gs = 2.5v) is required for applications that work close to this voltage. when these mosfets are used, make sure that the input supply to the LTC3809 is less than the absolute maximum mosfet v gs rating, which is typically 8v. the p-channel mosfets on-resistance is chosen based on the required load current. the maximum average load current i out(max) is equal to the peak inductor current minus half the peak-to-peak ripple current i ripple . the LTC3809s current comparator monitors the drain-to- source voltage v ds of the top p-channel mosfet, which is sensed between the v in and sw pins. the peak induc- tor current is limited by the current threshold, set by the voltage on the i th pin, of the current comparator. the voltage on the i th pin is internally clamped, which limits the maximum current sense threshold v sense(max) to approximately 125mv when iprg is ? oating (85mv when iprg is tied low; 204mv when iprg is tied high). the output current that the LTC3809 can provide is given by: i v r i out max sense max ds on ripple () () () ? = 2 where i ripple is the inductor peak-to-peak ripple current (see inductor value calculation). a reasonable starting point is setting ripple current i ripple to be 40% of i out(max) . rearranging the above equation yields: r v i for duty cycle ds on max sense max out max () () () ?% = < 5 6 20 however, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of r ds(on) to provide the required amount of load current: rsf v i ds on max sense max out max () () () ?? = 5 6 where sf is a scale factor whose value is obtained from the curve in figure 1. these must be further derated to take into account the signi? cant variation in on-resistance with temperature. the following equation is a good guide for determining the required r ds(on)max at 25c (manufacturers speci? ca- tion), allowing some margin for variations in the LTC3809 and external component values: rsf v i ds on max sense max out max t () () () ?.? ? ? = 5 6 09 the t is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/c, as shown in figure 2. junction-to-case temperature t jc is about 10c in most applications. for a maximum ambi- ent temperature of 70c, using 80c ~ 1.3 in the above equation is a reasonable choice. the n-channel mosfets on resistance is chosen based on the short-circuit current limit (i sc ). the LTC3809s short-circuit current limit comparator monitors the drain- to-source voltage v ds of the bottom n-channel mosfet, which is sensed between the gnd and sw pins. the
LTC3809 13 3809fc applications information short-circuit current sense threshold v sc is set approxi- mately 90mv when iprg is ? oating (60mv when iprg is t i e d l o w ; 15 0 mv w h e n i p r g i s t i e d h i g h). t h e o n - r e s i s t a n c e of n-channel mosfet is determined by: r v i ds on max sc sc peak () () = the short-circuit current limit (i sc(peak) ) should be larger than the i out(max) with some margin to avoid interfering with the peak current sensing loop. on the other hand, in order to prevent the mosfets from excessive heating and the inductor from saturation, i sc(peak) should be smaller than the minimum value of their current ratings. a reasonable range is: i out(max) < i sc(peak) < i rating(min) therefore, the on-resistance of n-channel mosfet should be chosen within the following range: << v i r v i sc rating min ds on sc out max () () () where v sc is 90mv, 60mv or 150mv with iprg being ? oated, tied to gnd or v in respectively. the power dissipated in the mosfet strongly depends on its respective duty cycles and load current. when the LTC3809 is operating in continuous mode, the duty cycles for the mosfets are: top p-channel duty cycle = bottom n-channel duty cycle = v v vv v out in in out in ? the mosfet power dissipations at maximum output current are: p v v irv icf p vv v ir top out in out max t ds on in out max rss bot in out in out max t ds on =+ = ??? ? ??? ? ??? () () () () () 22 2 2 both mosfets have i 2 r losses and the p top equation includes an additional term for transition losses, which are largest at high input voltages. the bottom mosfet losses are greatest at high input voltage or during a short-circuit when the bottom duty cycle is 100%. the LTC3809 utilizes a non-overlapping, anti-shoot- through gate drive control scheme to ensure that the p- and n-channel mosfets are not turned on at the same time. to function properly, the control scheme requires that the mosfets used are intended for dc/dc switching applications. many power mosf ets, particularly p-channel mosfets, are intended to be used as static switches and therefore are slow to turn on or off. reasonable starting criteria for selecting the p-channel mosfet are that it must t ypically have a gate charge (q g ) less than 25nc to 30nc (at 4.5v gs ) and a turn-off delay (t d(off) ) of less than approximately 140ns. however, due to differences in test and speci? cation methods of various mosfet manufacturers, and in the variations in q g and t d(off) with gate drive (v in ) voltage, the p-channel mosfet ultimately should be evaluated in the actual LTC3809 application circuit to ensure proper operation. shoot-through between the p-channel and n-channel mosfets can most easily be spotted by monitoring the input supply current. as the input supply voltage increases, if the input supply current increases dramatically, then the likely cause is shoot-through. note that some mosfets junction temperature (c) C50 r t normalized on resistance 1.0 1.5 150 3809 f02 0.5 0 0 50 100 2.0 figure 2. r ds(on) vs temperature
LTC3809 14 3809fc that do not work well at high input voltages (e.g., v in > 5v) may work ? ne at lower voltages (e.g., 3.3v). selecting the n-channel mosfet is typically easier, since for a given r ds(on) , the gate charge and turn-on and turn-off delays are much smaller than for a p-channel mosfet. operating frequency and synchronization the choice of operating frequency, f osc , is a trade-off between ef? ciency and component size. low frequency operation improves ef? ciency by reducing mosfet switching losses, both gate charge loss and transition loss. however, lower frequency operation requires more inductance for a given amount of ripple current. the internal oscillator for the LTC3809s controller runs at a nominal 550khz frequency when the plllpf pin is left ? oating and the sync/mode pin is not con? gured for spread spectrum operation. pulling the plllpf to v in selects 750khz operation; pulling the plllpf to gnd selects 300khz operation. alternatively, the LTC3809 will phase-lock to a clock signal applied to the sync/mode pin with a frequency between 250khz and 750khz (see phase-locked loop and frequency synchronization). to further reduce emi, the nominal 550khz frequency will be spread over a range with frequencies between 460khz and 635khz when spread spectrum modulation is enabled (see spread spectrum modulation with sync/mode and plllpf pins). inductor value calculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductors peak-to-peak ripple current: i v v vv fl ripple out in in out osc = ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. thus, highest ef? ciency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a speci? ed maximum, the inductor should be chosen according to: l vv fi v v in out osc ripple out in ? ? ? burst mode operation considerations the choice of r ds(on) and inductor value also determines the load current at which the LTC3809 enters burst mode operation. when bursting, the controller clamps the peak inductor current to approximately: i v r burst peak sense max ds on () () () ? = 1 4 the corresponding average current depends on the amount of ripple current. lower inductor values (higher i ripple ) will reduce the load current at which burst mode operation begins. the ripple current is normally set so that the inductor cur- rent is continuous during the burst periods. therefore, i ripple i burst(peak) this implies a minimum inductance of: l vv fi v v min in out osc burst peak out in ? ? ? () a smaller value than l min could be used in the circuit, although the inductor current will not be continuous during burst periods, which will result in slightly lower ef? ciency. in general, though, it is a good idea to keep i ripple comparable to i burst(peak) . inductor core selection once the value of l is known, the type of inductor must be selected. high ef? ciency converters generally cannot a f f o r d t h e c o r e l o s s f o u n d i n l o w c o s t p o w d e r e d i r o n c o r e s , forcing the use of more expensive ferrite, molypermalloy or kool m ? c or e s. a c tual c or e los s is indep enden t o f c or e applications information
LTC3809 15 3809fc size for a ? xed inductor value, but is very dependent on the inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are pre- ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that i n d u c t a n c e c o l l a p s e s a b r u p t l y w h e n t h e p e a k d e s i g n c u r r e n t is exceeded. core saturation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but is more expensive than ferrite. a reasonable compromise from the same manufacturer is kool m. toroids are very space ef? cient, especially when several layers of wire can be used, while inductors wound on bobbins are generally easier to sur- face mount. however, designs for surface mount that do not increase the height signi? cantly are available from coiltronics, coilcraft, dale and sumida. schottky diode selection (optional) the schottky diode d in figure 11 conducts current dur- ing the dead time between the conduction of the power mosfets. this prevents the body diode of the bottom n-channel mosfet from turning on and storing charge during the dead time, which could cost as much as 1% in ef? ciency. a 1a schottky diode is generally a good size for most LTC3809 applications, since it conducts a relatively small average current. larger diode results in additional transition losses due to its larger junction capacitance. this diode may be omitted if the ef? ciency loss can be tolerated. c in and c out selection in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle (v out /v in ). to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: c in re ? ?? / quiredi i vvv v rms max out in out in () 12 this formula has a maximum value at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet the size or height requirements in the design. due to the high operating frequency of the LTC3809, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering. the output ripple ( v out ) is approximated by: ? + ? ? ? ? ? ? v i esr fc out ripple out ? ?? 1 8 where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increase with input voltage. setting output voltage the LTC3809 output voltage is set by an external feed- back resistor divider carefully placed across the output, as shown in figure 3. the regulated output voltage is determined by: vv r r out b a =+ ? ? ? ? ? ? 06 1 .? applications information
LTC3809 16 3809fc for most applications, a 59k resistor is suggested for r a . in applications where minimizing the quiescent current is critical, r a should be made bigger to limit the feedback divider current. if r b then results in ver y high impedance, it may be bene? cial to bypass r b with a 50pf to 100pf capacitor c ff . run and soft-start functions the LTC3809 has a low power shutdown mode which is controlled by the run pin. pulling the run pin below 1.1v puts the LTC3809 into a low quiescent current shutdown mode (i q = 9a). releasing the run pin, an internal 0.7a (at v in = 4.2v) current source will pull the run pin up to v in , which enables the controller. the run pin can be driven directly from logic as showed in figure 4. once the controller is enabled, the start-up of v out is controlled by the internal soft-start, which slowly ramps the positive reference to the error ampli? e r f r o m 0 v t o 0 . 6 v, allowing v out to rise smoothly from 0v to its ? nal value. the default internal soft-start time is around 1ms. i s a n e d g e s e n si t i ve di gi t a l t y p e t h a t pr ov i d e s z er o d e gr e e s phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complementary current sources that charge or discharge the external ? lter network connected to the plllpf pin. the relationship between the voltage on the plllpf pin and operating frequency, when there is a clock signal applied to sync/ mode, is shown in figure 5 and speci? ed in the electrical characteristics table. note that the LTC3809 can only be synchronized to an external clock whose frequency is within range of the LTC3809s internal vco, which is nominally 200khz to 1mhz. this is guaranteed, over temperature and process variations, to be between 250khz and 750khz. a simpli? ed block diagram is shown in figure 6. applications information LTC3809 v fb v out r b c ff r a 3809 f03 figure 3. settling output voltage 3.3v or 5v 3809 f04 LTC3809 run LTC3809 run figure 4. run pin interfacing phase-locked loop and frequency synchronization the LTC3809 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. this allows the turn-on of the external p-channel m o s f e t t o b e l o c k e d t o t h e r i s i n g e d g e o f a n e x t e r n a l c l o c k signal applied to the sync/mode pin. the phase detector plllpf pin voltage (v) 0.2 0 frequency (khz) 0.7 1.2 1.7 3809 f05 2.2 200 400 600 800 1000 1200 digital phase/ frequency detector oscillator 2.4v r lp c lp 3809 f06 plllpf external oscillator sync/ mode figure 5. relationship between oscillator frequency and voltage at the plllpf pin when synchronizing to an external clock figure 6. phase-locked loop block diagram
LTC3809 17 3809fc if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced con- tinuously from the phase detector output, pulling up the plllpf pin. when the external clock frequency is less than f osc , current is sunk cont inuously, pulling down the plllpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the plllpf pin is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the ? lter capacitor c lp holds the voltage. the loop ? lter components, c lp and r lp , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. the ? lter components c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 2200pf to 0.01f. typically, the external clock (on sync/mode pin) input high level is 1.6v, while the input low level is 1.2v. table 1 summarizes the different states in which the plllpf pin can be used. table 1. the states of the plllpf pin plllpf pin sync/mode pin frequency 0v dc voltage (<1.2v or v in ) 300khz floating dc voltage (<1.2v or v in ) 550khz v in dc voltage (<1.2v or v in ) 750khz rc loop filter clock signal phase-locked to external clock filter caps dc voltage (>1.35v and LTC3809 + + r6 r5 1f v out v aux c out l1 1:n sync/mode bg sw tg 3809 f07 v in figure 7. auxilliary output loop connection spread spectrum modulation with sync/mode and plllpf pins switching regulators, which operate at ? xed frequency, conduct electromagnetic interference (emi) to their down- stream load(s) with high spectral power density at this fundamental and harmonic frequencies. the peak energy
LTC3809 18 3809fc can be lowered and distributed to other frequencies and their harmonics by modulating the pwm frequency. the LTC3809s switching noise (at 550khz) is spread between 460khz and 635khz in spread spectrum modulation opera- tion. figure 8 shows the spectral plots of the output (v out ) noise with/without spread spectrum modulation. note the signi? cant reduction in peak output noise (>20dbm). the spread spectrum modulation operation of the LTC3809 is enabled by setting sync/mode pin to a dc voltage between 1.35v and several hundred mv below v in by tying a resistor between sync/mode and v in . table 2 summarizes the different states in which the sync/mode pin can be used. table 2. the states of the sync/mode pin sync/mode pin condition gnd (0v to 0.35v) forced continuous mode current reversal allowed v fb (0.45v to 1.2v) pulse-skipping mode no current reversal allowed resistor to v in (1.35v to v in C 0.5v) spread spectrum modulation pulse skipping at light loads no current reversal allowed v in burst mode operation no current reversal allowed feedback resistors regulate an auxiliary winding external clock signal enable phase-locked loop (synchronize to external clock) pulse skipping at light load no current reversal allowed fault condition: short-circuit and current limit if the LTC3809s load current exceeds the short-circuit current limit (i sc ), which is set by the short-circuit sense threshold ( v sc ) and the on resistance (r ds(on) ) of bottom n-channel mosfet, the top p-channel mosfet is turned off and will not be turned on at the next clock cycle unless the load current decreases below i sc . in this case, the controllers switching frequency is decreased and the output is regulated by short-circuit (current limit) protection. in a hard short (v out = 0v), the top p-channel mosfet is turned off and kept off until the short-circuit condition is cleared. in this case, there is no current path from input supply (v in ) to either v out or gnd, which prevents excessive mosfet and inductor heating. low input supply voltage although the LTC3809 can function down to below 2.4v, the maximum allowable output current is reduced as v in decreases below 3v. figure 9 shows the amount of change as the supply is reduced down to 2.4v. also shown is the effect on v ref . applications information v out spectrum without spread spectrum modulation start freq: 400khz rbw: 100hz stop freq: 700khz noise (dbm) C10dbm/div 3809 f08a v out spectrum with spread spectrum modulation (c ssm = 2200pf) figure 8. spectral response of spread spectrum modulation start freq: 400khz rbw: 100hz stop freq: 700khz noise (dbm) C10dbm/div 3809 f08b
LTC3809 19 3809fc minimum on-time considerations minimum on-time, t on(min) is the smalles t amoun t of time that the LTC3809 is capable of turning the top p-channel mosfet on. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle and high frequency applications may approach the minimum on-time limit and care should be taken to ensure that: t v fv on min out osc in () ? < if the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3809 will begin to skip cycles (unless forced continuous mode is selected). the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. the minimum on- time for the LTC3809 is typically about 210ns. however, as the peak sense voltage (i l(peak ) ? r ds(on) ) decreases, the minimum on-time gradually increases up to about 260ns. this is of particular concern in forced continu- ous applications with low ripple current at light loads. if forced continuous mode is selected and the duty cycle falls below the minimum on time requirement, the output will be regulated by overvoltage protection. ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is applications information input voltage (v) 75 normalized voltage or current (%) 85 95 105 80 90 100 2.2 2.4 2.6 2.8 3809 f09 3.0 2.1 2.0 2.3 2.5 2.7 2.9 v ref maximum sense voltage figure 9. line regulation of v ref and maximum sense voltage limiting ef? ciency and which change would produce the most improvement. ef? ciency can be expressed as: ef? ciency = 100% C (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3809 circuits: 1) LTC3809 dc bias current, 2) mosfet gate-charge current, 3) i 2 r losses and 4) transition losses. 1) the v in (pin) current is the dc supply current, given in the electrical characteristics, which excludes mosfet driver currents. v in current results in a small loss that increases with v in . 2) mosfet gate-charge current results from switching the gate capacitance of the power mosfet. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in , which is typically much larger than the dc supply current. in continuous mode, i gatechg = f ? q p . 3) i 2 r losses are calculated from the dc resistances of the mosfets, inductor and/or sense resistor. in continuous mode, the average output current ? ows through l but is chopped between the top p-channel mosfet and the bottom n-channel mosfet. the mosfet r ds(on) mul- tiplied by duty cycle can be summed with the resistance of l to obtain i 2 r losses. 4) transition losses apply to the external mosfet and increase with higher operating frequencies and input voltages. transition losses can be estimated from: transition loss = 2 ? v in 2 ? i o(max) ? c rss ? f other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shif ts by an amount
LTC3809 20 3809fc applications information equal to ( i load ) ? (esr), where esr is the effective se- ries resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the i th series r c -c c ? lter (see functional diagram) sets the dominant pole-zero loop compensation. the i th external components showed in the ? gure on the ? rst page of this data sheet will provide adequate compen- sation for most applications. the values can be modi? ed slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the ? nal pc layout is done and the particular output capacitor type and value have been determined. the output capacitor needs to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability. the gain of the loop will be increased by increas- ing r c and the bandwidth of the loop will be increased by decreasing c c . the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25) ? (c load ). thus a 10f capacitor would be require a 250s rise time, limiting the charging current to about 200ma. design example as a design example, assume v in will be operating from a maximum of 4.2v down to a minimum of 2.75v (powered by a single lithium-ion battery). load current requirement is a maximum of 2a, but most of the time it will be in a standby mode requiring only 2ma. ef? ciency at both low a n d h i g h l o a d c u r r e n t s i s i m p o r t a n t . b u r s t m o d e o p e r a t i o n at light loads is desired. output voltage is 1.8v. the iprg pin will be left ? oating, so the maximum current sense threshold v sense(max) is approximately 125mv. maximumduty cycle v v out in min = () .% = 65 5 from figure 1, sf = 82%. rsf v i ds on max sense max out max t () () () ?.? ? ? . = = 5 6 09 0032 a 0.032 p-channel mosfet in si7540dp is close to this value. the n-channel mosfet in si7540dp has 0.017 r ds(on) . the short circuit current is: i mv a sc = = 90 0 017 53 . . so the inductor current rating should be higher than 5.3a. the plllpf pin will be left ? oating, so the LTC3809 will operate at its default frequency of 550khz. for continuous burst mode operation with 600ma i ripple , the required minimum inductor value is: l v khz ma v v h min =? ? ? ? ? ? ? = 18 550 600 1 18 275 188 . ? ? . . . a 6a 2.2h inductor works well for this application. c in will require an rms current rating of at least 1a at temperature. a c out with 0.1 esr will cause approxi- mately 60mv output ripple.
LTC3809 21 3809fc applications information pc board layout checklist when laying out the printed circuit board, use the following checklist to ensure proper operation of the LTC3809. ? the power loop (input capacitor, mosfet, inductor, output capacitor) should be as small as possible and isolated as much as possible from LTC3809. ? put the feedback resistors close to the v fb pins. the i th compensation components should also be very close to the LTC3809. ? the current sense traces should be kelvin connections right at the p-channel mosfet source and drain. ? keeping the switch node (sw) and the gate driver nodes (tg, bg) away from the small-signal components, es- pecially the feedback resistors, and i th compensation components. 10f s 2 v in 2.75v to 8v v out 2.5v (5a at 5v in ) mp si7540dp mn si7540dp 3809 f10 2 1 6 4 3 9 8 10 7 5 11 l 1.5h r ith 15k 187k 59k l: vishay ihlp-2525cz-01 c out : sanyo 4tpb150mc c ith 220pf 100pf c out 150f sync/mode v in plllpf iprg i th v fb tg sw bg run gnd LTC3809edd + 10f s 2 v in 2.75v to 8v v out 1.8v (5a at 5v in ) mp si7540dp mn si7540dp d opt 3809 f11 2 1 6 4 3 9 8 10 7 5 11 10k l 1.5h 15k 118k 100pf 59k l: vishay ihlp-2525cz-01 d: on semi mbrm120l (optional) 470pf 100pf 10nf c out 22f s 2 sync/mode v in plllpf iprg i th v fb tg sw bg run gnd LTC3809edd figure 11. synchronizable dc/dc converter with ceramic output capacitors figure 10. 550khz, synchronizable dc/dc converter with internal soft-start
LTC3809 22 3809fc typical applications dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.115 typ 2.38 p 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd10) dfn 1103 0.25 p 0.05 2.38 p 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p 0.05 (2 sides) 2.15 p 0.05 0.50 bsc 0.675 p 0.05 3.50 p 0.05 package outline 0.25 p 0.05 0.50 bsc
LTC3809 23 3809fc information furnished by linear technology corpor ation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s . package description msop (mse) 0908 rev c 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004) 0.1016 0.0508 (.004 .002) mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev c) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref
LTC3809 24 3809fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 1108 rev c ? printed in usa related parts typical application synchronous dc/dc converter with spread spectrum modulation c in 22f v in 3.3v v out 2.5v 2a mp si3447bdv mn si3460dv 3809 ta04 2 1 4 3 9 8 10 7 5 11 l 1.5h 15k 300k 187k 59k l: vishay ihlp-2525cz-01 470pf 2200pf 100pf 1000pf c out 22f synch/mode v in plllpf 6 iprg i th v fb tg sw bg run gnd LTC3809edd part number description comments ltc1628/ltc3728 dual high ef? ciency, 2-phase synchronous step down controllers constant frequency, standby, 5v and 3.3v ldos, v in to 36v, 28-lead ssop ltc1735 high ef? ciency synchronous step-down controller burst mode operation, 16-pin narrow ssop , fault protection, 3.5v v in 36v ltc1778 no r sense , synchronous step-down controller current mode operation without sense resistor, fast transient response, 4v v in 36v ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out 0.8v, i q = 60a, i sd = <1a, ms package ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out 0.8v, i q = 60a, i sd = <1a, tssop-16e package ltc3416 4a, 4mhz, monolithic synchronous step-down regulator tracking input to provide easy supply sequencing, 2.25v v in 5.5v, 20-lead tssop package ltc3418 8a, 4mhz, synchronous step-down regulator tracking input to provide easy supply sequencing, 2.25v v in 5.5v, qfn package ltc3708 2-phase, no r sense , dual synchronous controller with output tracking constant on-time dual controller, v in up to 36v, very low duty cycle operation, 5mm 5mm qfn package ltc3736/ltc3736-2 2-phase, no r sense , dual synchronous controller with output tracking 2.75v v in 9.8v, 0.6v v out v in , 4mm 4mm qfn ltc3736-1 low emi 2-phase, dual synchronous controller with output tracking integrated spread spectrum for 20db lower noise, 2.75v v in 9.8v ltc3737 2-phase, no r sense , dual dc/dc controller with output tracking 2.75v v in 9.8v, 0.6v v out v in , 4mm 4mm qfn ltc3772 micropower no r sense step-down dc/dc controller 2.75v v in 9.8v, 3mm 2mm dfn or 8-lead sot-23, 550khz, i q = 40a, current mode ltc3776 dual, 2-phase, no r sense synchronous controller for ddr/qdr memory termination provides v ddq and v tt with one ic, 2.75v v in 9.8v, adjustable constant frequency with pll up to 850khz, spread spectrum operation, 4mm 4mm qfn and 24-lead ssop packages ltc3808 low emi, synchronous controller with output tracking 2.75v v in 9.8v, 4mm 3mm dfn, spread spectrum for 20db lower peak noise LTC3809-1 no r sense synchronous controller with output tracking 2.75v v in 9.8v, 3mm 3mm dfn and 10-lead msope packages polyphase is a trademark of linear technology corporation.

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